https://www.comfilewiki.co.kr/en/ 2026-05-01T12:00:21+00:00 https://www.comfilewiki.co.kr/en/ https://www.comfilewiki.co.kr/en/lib/exe/fetch.php?media=wiki:logo.png text/html 2026-02-20T15:37:35+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.comfilewiki.co.kr/en/doku.php?id=cubloc:set_spi:index&rev=1771601855&do=diff Set Spi Set Spi clk, mosi, miso, mode clk port for clock output mosi port for data (Master output, Slave Input) miso port for data (Master input, Slave output) mode communication mode bit 3: 0 = MSB start, 1 = LSB start bit 2: 0 = wait at clock LOW, 1 = wait at clock HIGH